Zen 4c For Edge-Optimized Server Chips

AMD today is launching the 4th and last member of its 4 ^th generation EPYC processor household, the EPYC 8004 series. Formerly divulged under the codename Siena, the EPYC 8004 series is AMD’s affordable sub-set of EPYC CPUs, focused on the telco, edge, and other rate and efficiency-sensitive marketing sectors. Based upon the exact same Zen4c cores as Bergamo, Siena is essentially Bergamo-light, utilizing the exact same hardware to provide server processors with in between 8 and 64 CPU cores.

First revealed by AMD last summer season at Financial Expert Day 2022, Siena is AMD’s very first devoted entry into the telco, networking, and edge market. Compared to AMD’s general-purpose Genoa chips (EPYC 9004), Siena uses less CPU cores and lower efficiency in general, rather enhancing the chips and platform for lower expenses and much better energy performance for usage in non-datacenter environments. More broadly speaking, Siena is functionally the long-awaited low-end sector of the 4 ^th generation EPYC stack.

Unlike the launch of the previous 3 4 ^th generation EPYC sectors– Genoa, Genoa-X, and Bergamo— the launch of Siena is a lower-key affair. Besides the decreased enjoyment that features the launch of lower-end hardware, there is, strictly speaking, no brand-new silicon associated with this launch. Siena is consisted of the exact same 5nm Zen 4c core complex die (CCD) chiplets as Bergamo, which are coupled with AMD’s one and just 6nm EPYC I/O Pass Away (IOD). As an outcome, the EPYC 8004 household isn’t a lot brand-new hardware as it is a brand-new setup of existing hardware– about half of a Bergamo, offer or take.

Which half Bergamo example isn’t almost CPU cores; it uses to the remainder of the platform too. Highlighting the entry-level nature of the Siena platform, Siena ships with less DDR5 memory channels and less I/O lanes than its quicker, fancier equivalent. Siena just uses 6 channels of DDR5 memory, below 12 channels for other EPYC parts, and 96 lanes of PCIe Gen 5 rather of 128 lanes. As an outcome, while Siena is still a real Zen 4 part through and through (right on down to AVX-512 assistance), it’s general a significantly lighter-weight platform than the other EPYC relative.

However even without brand-new silicon to mention, Siena is still bringing some hardware modifications to the AMD community. For the launch of their light-weight server processor, AMD is presenting a brand-new server socket: Socket SP6. Making the most of the lower variety of I/O lanes and memory channels utilized by Siena– not to discuss the smaller sized physical footprint of the decreased variety of chiplets– socket SP6 chips are physically smaller sized and function less LGA pads, developed to enable appropriately less expensive motherboards.

The LGA SP6 chips determine 58.5 x 75.4 mm, below 72 x 75.4 mm for SP5, or have to do with 81% of the size. In regards to pin counts, we’re taking a look at a still large 4844 pins, which is still below the 6096 pins utilized in SP5. In general, it does produce a little an odd scenario to have the only non-SP5 EPYC be the only EPYC with no brand-new silicon in it, however we think this will not be the only location we see SP6 over the coming years.

Entirely, AMD is presenting Siena with a substantial stack of 12 chips. There are basically 6 tiers of chips, each separated by the variety of Zen 4c CPU cores offered, with each tier offered in both a conventional chip or a set power Network Equipment-Building System (NEBS) friendly setup, which uses a larger temperature level variety tolerance and is developed for releases in less regulated conditions.

The flagship Siena part is the EPYC 8534P, which uses 64 Zen 4c cores utilizing 4 Zen 4c CCDs. The default TDP on this part is 200 watts, with a cTDP series of 115W as much as 225W. For all useful functions this is half of an EPYC Bergamo 9754, using half as numerous CPU cores, half as much L3 cache, half as much memory bandwidth, and depending upon how to call in the cTDP, around half the TDP. Like the Bergamo household, these chips are focused on clients who require more CPU cores more than they require top-tier single-threaded efficiency, with the Zen 4c CPU cores peaking at simply 3.1 GHz when increasing, and performing at a base clockspeed of 2.3 GHz. The 8534P’s NEBS equivalent, the 8534PN, uses the exact same chip setup at a 175W repaired TDP, and a lower base clockspeed of 2.0 GHz, all in exchange for a larger -5 C to +85 C operating variety.

At the other end of the spectrum is the EPYC 8024P. This part includes simply 8 CPU cores– AMD is utilizing a single, half-enabled Zen 4c CCD here– with the L3 cache reduced to that of a single CCD, at the same time the complete 6 channels of DDR5 memory and 96 PCIe lanes stay. This 8 core part has a base TDP of 90W, though that can be adapted to be in between 70W and 100W.

Otherwise, given that AMD is utilizing the exact same IOD as their other EPYC parts, much of the restrictions and compromises with those parts stay. The greatest supported memory speed is DDR5-4800, which can just be struck with 1 DPC. And not all of the PCie lanes can be changed to CXL mode– in this case, simply 48 lanes. Showing the lower-cost nature of the Siena platform, 3DS RDIMMs are not supported here, suggesting that the platform’s optimum memory capability is 12x96GB (1.152 TB) of DDR5 RDIMMs.

At very first blush, I was amazed to see that AMD kept the exact same large EPYC IOD for their budget plan server part. However AMD has actually had almost a year to stock faulty IODs for salvage functions. Probably, a smaller sized IOD would transcend from an energy performance viewpoint, however that is reversed by the reality that AMD would require to invest the time taping out a brand-new IOD for what is implied to be an inexpensive part that gains from silicon reuse. I would be a bit more shocked if AMD does not do a smaller sized IOD for future generations of chips in this item sector, however as has actually held true given that the start of AMD’s EPYC journey, they are taking things gradually and gradually here as they broaden their server CPU offerings.

In any case, with the Siena/EPYC 8004 lineup, AMD is seeking to drive house the expense argument for these chips, specifically compared to Intel’s 4 ^th generation Xeon (Sapphire Rapids) lineup. Because there’s no brand-new silicon here, Siena does not substantially alter any of the calculus there, however Intel’s concentrate on accelerators versus AMD’s concentrate on full-scale CPU efficiency indicates that AMD can bring a great deal of CPU cores to bear even in less expensive setups. Which, in work that can’t make the most of Intel’s accelerators, AMD thinks provides a substantial edge.

As constantly, supplier numbers need to be taken with a grain of salt. However AMD is fairly positive in the capability of their chips to hold the lead in perf-per-watt, specifically when compared to a Xeon with a comparable variety of cores.

Covering things up, according to AMD, Siena chips are offered now. The market price vary from $5,450 to $409 in 1,000 system amounts– while AMD’s larger partners generally improve offers than that. Mentioning which, much of the typical suspects in the server area are releasing brand-new platforms in the coming weeks based upon Siena, with Dell, Lenovo, and Supermicro all flaunting edge-optimized systems.